|
- ---------------------------------------------------------------------
- -- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
- -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
- -- DATE CREATED: 6/6/02
- -- FILENAME: plasma_if.vhd
- -- PROJECT: Plasma CPU core
- -- COPYRIGHT: Software placed into the public domain by the author.
- -- Software 'as is' without warranty. Author liable for nothing.
- -- DESCRIPTION:
- -- This entity divides the clock by two and interfaces to the
- -- Altera EP20K200EFC484-2X FPGA board.
- -- Xilinx Spartan-3 XC3S200FT256-4 FPGA.
- ---------------------------------------------------------------------
- library ieee;
- use ieee.std_logic_1164.all;
- --use work.mlite_pack.all;
-
- entity plasma_if is
- port(clk_in : in std_logic;
- reset : in std_logic;
-
- uart_console_read : in std_logic;
- uart_console_write : out std_logic;
-
- spi_miso : out std_logic;
- spi_mosi :in std_logic;
- spi_clk : in std_logic;
- spi_cs : in std_logic;
-
- gpio0_out : out std_logic_vector(2 downto 0);
- gpioA_in : in std_logic_vector(1 downto 0);
- pwm_out : out std_logic_vector(23 downto 0));
- end; --entity plasma_if
-
-
- architecture logic of plasma_if is
-
- component plasma
- generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
- log_file : string := "UNUSED");
- port(clk : in std_logic;
- clk66 : in std_logic;
- reset : in std_logic;
-
- uart_write : out std_logic;
- uart_read : in std_logic;
-
- address : out std_logic_vector(31 downto 2);
- byte_we : out std_logic_vector(3 downto 0);
- data_write : out std_logic_vector(31 downto 0);
- data_read : in std_logic_vector(31 downto 0);
- mem_pause_in : in std_logic;
-
- gpio0_out : out std_logic_vector(31 downto 0);
- gpioA_in : in std_logic_vector(31 downto 0);
- pwm_out : out std_logic_vector(23 downto 0);
-
- spi_miso : out std_logic;
- spi_mosi : in std_logic;
- spi_clk : in std_logic;
- spi_cs : in std_logic);
- end component; --plasma
-
-
-
- signal clk_reg : std_logic;
- signal we_n_next : std_logic;
- signal we_n_reg : std_logic;
- signal mem_address : std_logic_vector(31 downto 2);
- signal data_write : std_logic_vector(31 downto 0);
- signal data_reg : std_logic_vector(31 downto 0);
- signal byte_we : std_logic_vector(3 downto 0);
- signal mem_pause_in : std_logic;
- signal gpio0_out_reg : std_logic_vector(31 downto 0);
- signal gpioA_in_reg : std_logic_vector(31 downto 0);
-
- signal uart_plasma_console_write : std_logic;
- signal uart_plasma_console_read : std_logic;
-
-
- signal consel : std_logic;
-
- begin --architecture
- --Divide 50 MHz clock by two
- clk_div: process(reset, clk_in, clk_reg, we_n_next)
- begin
- if reset = '0' then
- clk_reg <= '0';
- elsif rising_edge(clk_in) then
- clk_reg <= not clk_reg;
- end if;
- end process; --clk_div
-
- mem_pause_in <= '0';
- gpio0_out(2 downto 0)<=gpio0_out_reg(2 downto 0);
- gpioA_in_reg(1 downto 0)<=gpioA_in(1 downto 0);
- gpioA_in_reg(31 downto 2)<=(others=>'0');
-
- u1_plasma: plasma
- generic map (memory_type => "XILINX_16X",
- log_file => "UNUSED")
- PORT MAP (
- clk => clk_reg,
- clk66 => clk_in,
- reset => not reset,
- uart_write => uart_plasma_console_write,
- uart_read => uart_plasma_console_read,
-
- address => mem_address,
- byte_we => byte_we,
- data_write => data_write,
- data_read => data_reg,
- mem_pause_in => mem_pause_in,
-
- gpio0_out => gpio0_out_reg,
- gpioA_in => gpioA_in_reg,
- pwm_out => pwm_out,
- spi_mosi => spi_mosi,
- spi_miso => spi_miso,
- spi_clk => spi_clk,
- spi_cs => spi_cs
- );
-
- uart_console_write <=uart_plasma_console_write;
- uart_plasma_console_read <=uart_console_read;
-
-
- end; --architecture logic
|
